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Common Source Amplifier

Now that we have a [mildly] solid grasp on transistors equations and modeling them, let’s talk about actually using them to perform a function. There are three basic amplifiers we use, and they all have different use cases. In this post, I want to talk about the most obvious one, at least with respect to the word amplifier: the common source amplifier.

Not quite sure why Vdd is cut off at the top, but no big deal! Just another constant voltage. The name “common source” comes from the fact we ground the source of the transistor, meaning it’s stuck at the common voltage reference - zero volts.

The only node in this circuit that isn’t already defined is the one between the resistor and the transistor, so we’ll call that our output. Now, analyzing this could be really obnoxious, or it could be really simple, so let’s do the lazy one.

In order to use the small signal model from before, there’s a couple rules we need to follow. Obviously, we assume that the voltage sources $V_b$ and $V_{DD}$ are at the correct levels to ensure we always stay in saturation. We also have another slightly odd assumption - that the DC level won’t move. This makes sense, we’re biasing to some DC level, why would we change it? All this means is that the Vin signal is going to be moving at some non-zero speed, we’ll say 2kHz arbitrarily.

This means that our DC source ($V_b$ and $V_{dd}$) are going to be considered “shorts” at this frequency, so we’ll actually end up wrapping our resistor back around to ground. This puts it in parallel with the D-S connection of the transistor, which will make our life very easy.


Alright, now we have our small signal model ready to go. I didn’t draw the labels, but as a refresher, we have the gate in the top left at $V_{in}$, the source on bottom at ground, and the drain the top right at… something. Let’s solve for our drain voltage/current now.

We can combine the resistors into one resistor since they’re just in parallel, and it will have value $R_o || R_L$. The current source will pump out current at $g_m V_{in}$ flowing *downward* - direction is important! Then, with KCL at the top node, we get:

$$ i_{CS} + i_{R} = 0 $$ $$ i_{R} = -i_{CS} $$

So the voltage at the top node (the drain) is going to be just current times resistance, or:

$$V_{out} = V_{D} = -g_m V_{in} (R_o || R_L)$$

So this is what we call an inverting amplifier. As the input gets bigger, the output gets smaller, and vice versa. Don’t forget, this is just a small signal change! We still have our biased voltages, so it’s really that bias point with our new output ripple: $V_b + V_{out}$.

Let’s test it out in simulation! First, the real MOSFET:

* Common Source Amplifier
.model MOSN NMOS level=3

vdd res 0 DC 20
vb bias 0 dc 5
vin bias gate sin(0 0.1 1k)
r res drain 2k
m1 drain gate 0 0 MOSN W=1m

.tran 0.01m 5m
.options list node post


I set the bias voltage to 5V, and $V_{DD}$ to 20V. The input is a 0.1V sine wave at the gate, and I plotted it for two load resistors, a $2k\Omega$ and a $4k\Omega$. It’s pretty confusing to see them on the same graph, since the DC point moves quite a bit.


Looking at it with the averaged, or bias, removed, it’s far clearer how our result looks.


Now as a wrap up, let’s compare our small signal model to a real transistor. After all, a model is only good if it’s a close fit! I approximate the output resistance from the using the DC values ($V_{in}=0$). A simple DC solver will give me the drain voltage, then I can get everything else from there. Values shown as with RL = [2k 4k]:

$$ V_{ds} = [14.8, 9.6] $$

$$ R_o = V_{ds}/I_{ds}$$

$$ I_{ds} = (V_{dd} - V_{ds})/R_L = [2.6, 2.6]*10^{-3}$$

$$ R_o = [5.6, 3.7]*10^3 $$

Is it weird that the current is the same for changing load resistors? No! Current is dictated by the gate voltage, so it should be the same! I get $g_m$ from a parameter sweep - the derivation is a bit too dense for here - so just trust me $g_m$ = 1mA/V.

* Common Source Amplifier, Small Signal Model

vin gate 0 sin(0 0.1 1k)

* voltage-controlled current source
G1 drain 0 gate 0 1m
rl drain 0 2k
ro drain 0 5.6k

.tran 0.01m 5m
.options list node post


And here’s a plot showing the simulation results of both:


Alright, the gain ratio isn’t quite as accurate, but overall we get similar images. If we really wanted, we could get much more precise value for the current source and output resistance, but this will do for now. Instead of getting approximately 2x/4x, we get about 1.5x/2x. A little more tuning (better $g_m$, better $r_o$) and a little better layout (use capacitor to set $R_L$ independent of biasing) would go a long way, but this is a solid start.

P.S. All of these hold up for BJT too! Just replace the transistor and it’ll be very similar.