# Common Drain Amplifier

Now that we have a gain stage for our amplifiers, we need an isolating stage. I talked about loading effects before, specifically the dangers that happen when we just hook things up randomly. The solution shown there was quick and easy, just an op amp, but that’s not great for circuit design. The ideal solution to this problem is a circuit that gives us two things:

• Infinite input impedance (so all the voltage goes into our circuit)
• Zero output impedance (so all the voltage goes to our load)

While we can do this with an op amp, let’s try to do it with as few components as possible. The smallest we can get down to is just one transistor and one resistor! If we put a circuit together in the common drain configuration, we get the following schematic:

A quick few reminders about this schematic: there’s two grounds in this schematic. The triple-line ground is what I’ll call “earth ground” or exactly zero volts. The triangle ground is “AC-ground”, “small-signal ground”, or “relative ground”. What this means is that in reality, we have some DC bias voltage applied here in order to ensure the transistor is always in saturation. So instead of just having that sinusoidal voltage source applied to the gate of the NMOS, we have an additional DC voltage in series with it.

The goal of this is to ensure $V_{in} \approx V_{out}$. Let’s break it down to a small signal model and see if we can prove that:

The next step is to determine the input/output relationships. Looking at where the grounds are, we can see that the output resistor, load resistor, and current source are all in parallel. What does a dependent current source in parallel look like though? If we put a a voltage source into the gate, we can derive the following through KCL:

$$g_m (V_{in}-V_{out}) = \dfrac{V_{out}}{R_1||R_{ds}}$$

$$g_m V_{in} = V_{out} \left( \dfrac{1}{R_1 || R_{ds}} + g_m \right)$$

$$\dfrac{V_{out}}{V_{in}} = \dfrac{g_m}{g_m + \frac{1}{R_1 + R_{ds}}} \approx \dfrac{g_m}{g_m} = 1$$

Nice! We get a perfect voltage following, assuming that we have decently large on resistance (Rds) and load resistance (R1). Now let’s test it. Here’s our example netlist and results:

* Common Drain Amplifier

.model MOSN NMOS level=3

vdd drain 0 DC 20
vb bias 0 dc 7
vin bias gate sin(0 0.1 1k)

r source 0 5k
m1 drain gate source 0 MOSN W=4m

*.save @m1[gm]
.tran 0.01m 5m
.options list node post

.end


And let’s see what it looks like with a couple of different load resistors:

Not the greatest output waveform, so let’s remove those DC biases and just show the amplitudes (this is the equivalent of moving from “three-line/earth” ground to “relative/AC” ground).

Much closer to what we expected! There’s barely (maybe 10mV) difference between the different load resistors. Our equations showed that that the gain should basically be 1, and have minimal dependency on the load resistor. This holds true as long as

$$\dfrac{1}{R_{ds}||R_L} << 1$$

So as we increase $R_L$, the “true-r” that inequality becomes, and the better our approximation is. Solid results so far, now let’s validate our ideas with the model.

To calculate $r_{ds}$, I just did Ohm’s Law around the transistor for a DC simulation. $g_m$ was extracted from the simulation, but there’s plenty of other ways to calculate it manually (sweep $V_{in}$, measure $I_D$).

* Common Drain Amplifier, Small Signal Model

vin gate 0 sin(0 0.1 1k)

* voltage-controlled current source
G1 0 out gate 0 1m

rds 0 out 1.2k
rl out 0 5k

.tran 0.01m 5m
.options list node post
.end


The lines get pretty close, but overall the results seem accurate! The only small error in our model seems to be that small resistors induce some gain into the equation. Not much, but enough to make me want to double check the numbers I got, or stick with transistors for modeling. We know there can never be gain in the real transistor setup, as the denominator is always larger than the numerator… unless we feed this into a negative resistance stage.

Lots of work, but our definitions are validated! With just one device, we can turn a poor voltage source into a nearly perfect one. Now you can see where the nickname “source follower” comes from - the source voltage follows (mirrors) the gate voltage.