ECE598RPP Final Project

For my final project in ECE598RPP by Prof. Pilawa, I wanted to combine my interests in time-domain signal processing with low-voltage power management systems. My favorite work presented in the class was on multi-phase DC-DC regulation, specifically a paper dealing with asymmetric interleaving 1. They did some excellent work on recognizing that naive interleaving may not be the best solution (and definitely is not) for assymmetric loads due to varying the fundamental Fourier coefficients.

They implemented a solution using a microcontroller with an on-board look-up table (LUT) for each possible load setting, and would calculate the optimum phase delays from there. It was a neat solution, but it seemed a bit clunky to me. I was interested in finding a cleaner solution using time-domain control, since that is effectively the desired output.

The solution was, at a high-level, to use a delay-locked-loop (DLL) to provide clock generation. Coarse phase tuning would be done by selecting DLL nodes. From there, each phase would be passed to a digitally-controlled delay line (DCDL) to set precise phase tuning. A controller would monitor the output loads and set the DLL/DCDL parameters. Details and initial simulation results are presented in my report below.

  1. M. Schuck, A. D. Ho and R. C. N. Pilawa-Podgurski, “Asymmetric Interleaving in Low-Voltage CMOS Power Management With Multiple Supply Rails,” in IEEE Transactions on Power Electronics, vol. 32, no. 1, pp. 715-722, Jan. 2017. doi: 10.1109/TPEL.2016.2530783 ^